A Burst Mode PN Acquisition Processor for Direct Sequence Spread - Spectrum

ACKNOWLEDGMENT I would like to thank Dr. Charles Chien for his abundant amount of technical input in all of my research. I am also grateful for Dr. Chien's guidance and criticism on my scientific language and responsibilities. In addition, I would like to thank my adviser, Professor Rajeev Jain, for giving me the opportunity to work with a tremendous group of researchers. My thanks also extends to other members of my thesis committee: Professor Amongst my graduate student and staff colleagues, I would like to thank Vipin Agrawal for his patience and many long hours of discussions on general theories of communications and signal processing, and the meaning of life and project goals; Richard Au and Greg Bringer for their helpful insights on RF sections of a wireless radio and proofreading my thesis; Paul Lettieri for proofreading my thesis; In asynchronous and packet networks adopting direct sequence spread spectrum, a fast PN acquisition loop is essential. Rapid acquisition processors in burst transmissions can significantly reduce the amount of overhead used for preambles to achieve a higher network throughput. This thesis begins with some basic architectures for PN acquisition. The fundamentals of a noncoherent structure for PN acquisition are described mathematically for an additive white Gaussian noise channel. Simulation results are collected to verify theoretical analysis and performance trade-off for different architectures. To achieve a mean acquisition time of less than 10 bits over a wide range of chip-to-noise ratios, the matched filter acquisition architecture is selected. xii To synthesize the PN acquisition loop, current technologies in design automation are used. An overview of what entails in this design automation process is first explained. Then, the matched filter PN acquisition loop is described in RTL VHDL code. A logic synthesizer is used to map VHDL to standard cells in 0.5µm CMOS. The standard cell netlist is placed and routed using a commercial tool. With a clock frequency of 20 MHz, the estimated power dissipation is 140 mW at 3.3 volts and the estimated chip area is 4.6mm x 5.1mm.